The present invention generally relates to a method of fabricating a built-in chip type substrate containing a semiconductor chip.
Recently and continuing, performance of electronic apparatuses using semiconductor devices such as semiconductor chips is becoming higher and higher, and it is required to highly integrate and miniaturize substrates on which semiconductor chips are mounted.
For this purpose, built-in chip type substrates in which a semiconductor chip is embedded are proposed, and further a variety of structures are proposed for such substrates containing semiconductor chips.
When forming such built-in chip type substrates, it is necessary to form wirings connected to semiconductor chips. Density and fineness of the wirings connected to the semiconductor chips are becoming higher and higher.
[Patent Document #1]
Japanese Laid-open Publication 2001-217381
However, as the density and fineness of such wirings connected to semiconductor chips become higher, the above explained built-in chip type substrates have the following problem. The accuracy of connection between the wirings and the semiconductor chips is difficult to control and therefore throughput of the substrate is lowered due to connection failures.
The main cause of such connection failures is poor accuracy of exposure position in photolithographic processes for patterning wirings connected to semiconductor chips. Thus it is desired to improve the accuracy of positioning wirings, compared to conventional exposure accuracy.